Accessible PDF from the Ground Up! Karen McCall, mtn-i.info, Microsoft MVP Word. Phone: E-mail: [email protected] Web. SystemC: From the Ground Up David C. Black Jack Donovan Bill Bunton Anna Keist ○○SystemC: From the Ground. Read ebook Ebook download From the Ground Up: 28th Ed For Android Download file Download now.
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Hi, I have a copy of FTGU but I would like the PDF version so I can print off a copy to make notes on. My computer is too slow to download. PDF | Programming from the Ground Up uses Linux assembly language to teach new programmers the most important concepts in. c from the ground up is available in our book collection an online access to it is set as public SystemC: From the Ground Up Pdf mtn-i.info, mtn-i.info, .
Code will appear in monotype Courier font. User-selectable syntax items are in italics for emphasis. Repeated items may be indicated with an ellipsis … or subscripts.
The following is an example: Naur, P. Communications of the ACM, 3 5 , Occasionally, we will refer to a member function or method without the arguments. The terminology will be presented as the book progresses.
This change was the result of comments that the dotted circle was too hard to make out in some cases. We also removed arrows since in most cases, the meaning is not always clear2.
This convention is reserved for the SystemC library, and you should not use it in end-user code your code. About the Examples To introduce the syntax of SystemC and demonstrate its usage, we have filled this book with examples. Most examples are not real-world examples. Real examples become too cluttered too fast. The goal of these examples is to communicate Does an arrow convey calling direction i. Since many interfaces contain a mixture of calls, some input and some output, showing data flow direction is not very useful.
For the most part, we used a common theme of an automobile for the examples. By convention, we show syntax examples stylistically as if SystemC is a special language, which it is not.
We hope that this presentation style will help you apply SystemC on your first coding efforts.
It should also be noted that due to space limitations and to reduce clutter, we have omitted showing standard includes i. You may assume something such as the following is implied in most of the examples: We believe making the examples clear and brief warrants ignoring this common wisdom. A reader already familiar with SystemC will find this content to be a great reference.
Chapters 1 through 3 provide introductions and overviews of the language and its usage. Methodology is briefly discussed. We provide exercises at the end of Chapters 4 through 16 to reinforce the concepts presented in the text.
Chapters 16 through 18 strengthen the basic language concepts. In these chapters, readers will find discussions of areas to watch and understand when designing, writing, or using SystemC in a production environment.
For the student or engineer already familiar with SystemC, Chapters 4 through 13 will provide some interesting background and insights into the language. You can either skip or read these early chapters lightly to pick up more nuances of the language. The content here is not meant to be a complete description of the language. Chapters 14 through 18 provide intermediate to advanced material.
For the instructor, this book may provide part of an advanced undergraduate class on simulation or augment a class on systems design.
In most of the examples presented in the book, the authors show code fragments only so as to emphasize the points being made. Examples are designed to illustrate specific concepts, and as such are toy examples to simplify learning.
Complete source code for all examples and exercises is available for download from www. You will need this book to make best use of these files. As with most design languages, SystemC has evolved. Many research groups and EDA companies have contributed to the language.
A timeline of SystemC is included in Table 1. The language has evolved and is evolving to a true system design language that includes both software and hardware concepts. Open SystemC Initiative Several of the organizations that contributed heavily to the language development efforts realized very early that any new design language must be open to the community and not be proprietary. OSCI was formed to: This library adds support for modern high-level verification language concepts such as constrained randomization, introspection, and transaction recording.
This edition includes a chapter devoted to the SCV from a syntactic point of view. Additionally, sub-committees are studying such topics as synthesis subsets and formalizing terminology concerning levels of abstraction for transaction-level modeling TLM. This edition includes a chapter devoted to TLM and current activities. Nasib Naser, Synopsys Inc. We hope that we have corrected them all in this edition: These wonderful life partners despite misgivings about four wild-eyed engineers supported us cheerfully as we spent many hours researching, typing, discussing, and talking to ourselves while pacing around the house as we struggled to write this book over the past year.
We also acknowledge our parents who gave us the foundation for both our family and professional life. IEEE The Basic Unit of Design: The Basic Unit of Execution: Simulation Process Registering the Basic Process: Completing the Simple Design: Alternative Constructors: Simplified Simulation Engine Another Look at Concurrency and Time The SystemC Thread Process SystemC Events Catching Events for Thread Processes Zero-Time and Immediate Notifications Understanding Events by Way of Example The SystemC Method Process Catching Events for Method Processes Static Sensitivity for Processes Altering Initialization The SystemC Event Queue Spawn Options A Spawned Process Example Process Control Methods SystemC Signal Channels Resolved Signal Channels Direct Submodule Header-Only Implementation Direct Submodule Implementation Indirect Submodule Header-Only Implementation Indirect Submodule Implementation Contrasting Implementation Approaches The Need for Ports Simple SystemC Port Declarations Many Ways to Connect Port Connection Mechanics Accessing Ports From Within a Process Event Finders and Default Events The Interrupt, a Custom Primitive Channel The Heartbeat, a Custom Hierarchical Channel The Adaptor, a Custom Primitive Channel The Transactor, a Custom Hierarchical Channel Elaboration and Simulation Callbacks Programmable Structure Debugging and Signal Tracing Other Libraries: Names and Namespaces Standard Library Tidbits Closing Thoughts If you already know why you are studying SystemC, then you can jump ahead to Chapter 2.
If you are learning SystemC for a college course or because your boss says you must, then you may benefit from this chapter. SystemC is a system design and modeling language. Furthermore, the hardware and software are usually co-developed on a tight schedule with tight real-time performance constraints and stringent requirements for low power. Thorough functional and architectural verification is required to avoid expensive and sometimes catastrophic failures in the device. In some cases, these failures result in the demise of the company or organization designing the errant system.
The prevailing name for this concurrent and multidisciplinary approach to the design of complex systems is electronic system-level design or ESL. The drive for concurrent engineering through ESL has side effects that affect more than the design organizations of a company. ESL affects the basic business model of a company and how companies interact with their customers and with their suppliers. ESL happens by modeling systems at higher levels of abstraction than traditional methods used in the past.
Portions of the system model are subsequently iterated and refined, as needed. Black et al. The authors believe that SystemC is uniquely positioned to meet these requirements. We will discuss all these topics in more detail in the following sections. Many more multi-disciplinary trade-offs are required to optimize the hardware, the software, and the overall system performance. Modern electronic systems consist of many subsystems and components. ESL focuses primarily on hardware, software, and algorithms at the architectural level.
In modern systems, each of these disciplines has become more complex. Likewise, the interaction has become increasingly complex. Interactions imply that trade-offs between the domains are becoming more important for meeting customer requirements. System development teams find themselves asking questions like: These questions are not trivial and the list could go on and on. Systems are so complex, just deriving specifications from customer requirements has become a daunting task.
Hence, this task brings the need for higher levels of abstraction and executable specifications or virtual system prototypes.
Figure 1. The figure shows three sample designs from three generations: The bars for each generation imply the code complexity for four common levels of abstraction associated with system hardware design: Notice that Figure 1. It does not reflect the greater complexity of a system with several large chips integrated circuits or FPGAs and gigabytes of application software. Many stop-gap approaches are being applied, but the requirement for a fundamentally new approach is clear. Part of the reason for the drive for a shortened design cycle is the perceived need for a very fast product cycle in the marketplace.
This scenario describes a recent experience by one of the authors. If the scope of the new system is not reduced and the schedule is reduced, then additional resources are required.
In this scenario, a shorter design cycle actually requires more resources expenses. The project requires more communication between development groups because of concurrent design , more tools, more people, and more of everything. ESL and TLM are an approach to reduce the cost of development through more efficient communication and through reduced rework.
This person was known by a variety of titles such as system architect, chief engineer, lead engineer, or project engineer.
This guru may have been a software engineer, hardware engineer, or algorithm expert depending on the primary technology leveraged for the system. The complexity was such that this person could keep most or all of the details in his or her head.
This technical leader was able to use spreadsheets and paper-based methods to communicate thoughts and concepts to the rest of the team. In most cases, these trade-offs resulted in conceptual disconnects among the three groups. For example, cellular telephone systems consist of very complex algorithms, software, and hardware. Teams working on them have traditionally leveraged more rigorous but still ad-hoc methods.
The ad-hoc methods usually consist of a software-based model. The SAM is a communication vehicle between algorithm, hardware, and software groups. The model can be used for algorithmic refinement or used as basis for deriving hardware and software subsystem specifications.
The exact parameters modeled are specific to the system type and application, but the model is typically un-timed more on this topic in the following section. Typically, each team then uses a different language to refine the design for their portion of the system. The teams leave behind the original multidiscipline system model and in many cases, any informal communication among the groups. These techniques include processor development boards using a single-chip implementation of the processor.
These implementations were used on the SoC or embedded system, FPGA prototypes of algorithms, and hardware emulation systems, just to name a few. These techniques were focused on early development of software, usually the last thing completed before a system is deployed. The ESL approach uses these existing techniques.
ESL also leverages a virtual system prototype or a TLM model of the system to enable all the system design disciplines to work in parallel. This virtual system prototype is the common specification among the groups. The resulting Gantt chart is illustrated next in Fig. Even though all of the electronic system design organizations will finish their tasks earlier, the primary reason for ESL is earlier development of software. Even getting a product to market a month earlier can mean tens of millions of dollars of business to a company.
Not using ESL methods will likely result in the under-design or over-design of the system. Both of these results are not good. Under-design is obviously not good. The product may not operate fast enough, may not have long enough battery life, or just may not have the features required by the customer. Over-design is not as obvious, but it is not good either.
Over-design takes significantly more resources and time to achieve, and it adds a heavy cost to an organization.
In addition, over-designed products usually are more complex, more expensive to manufacture, and are not as reliable. The authors have significant anecdotal stories of under-design and over-design of systems.
Another company related how a significant function on a chip caused weeks of schedule slip for design and verification. However, the function was later found not to be used by the software. Things become even more interesting if a system, say a cell phone, are really a subsystem for the customer, who is a mobile phone and infrastructure provider. Now, the customer needs models very early in their design process and will be making system design trade-offs based on a model provided by the subsystem provider previously system.
In addition, the subsystem provider likely relies on third-party intellectual property. The subsystem cell phone supplier will then need a model of the intellectual property used in their subsystem very early in the development cycle to enable their design trade-offs. Customers up and down the value chain may now be making business decisions based on the type and quality of the model provided by their supplier. This hierarchy of reliance is fundamentally a different way of doing business.
The virtual system prototype may have different blocks or components or subsystems at different levels of abstraction for a particular task to be performed by one of the system disciplines.
Initially, most of the system may be very abstract for software development until the software team is reasonably sure of the functionality.
At this point, a more detailed model of the blocks that closely interact with the software can be introduced into the model. We will discuss TLM in much greater detail in the following section. To understand TLM, one must first have a terminology for describing abstraction levels. Secondly, one must understand the ways the models will probably be used the use cases. The basic concept states that refinement of the interface or communication of a logical block can be refined independently of functionality or algorithm of the logical block .
We have significantly modified his concept and presented the result in the figure below. The x-axis is the abstraction level of the model or logical block interface or communication.
The key thing to notice is that the functionality can be refined independent of the Interface and the reverse is also true. A logical block may be approximately timed AT for the model functionality.
The corresponding interface for the block may be pin and cycle accurate PCA. This type of block is many times referred to as a bus functional model for functional verification. This modeling use cases are graphically represented in the following figure: We will assume a 1. The timing diagram in Figure 1.
When first defining and modeling the system application, the exact bus-timing details do not affect the design decisions. All of the important information contained within the illustration is transferred between the bus devices as one event or transaction.
Further into the development cycle, the number of bus cycles may become important to define bus cycle-time requirements, etc. The information for each clock cycle of the bus is transferred as one transaction or event bus-arbitration or cycle-accurate computation models. When the bus specification is fully chosen and defined, the bus is modeled with a transaction or event per signal transition bus functional or RTL model. Of course, as more details are added, more events occur and the speed of the model execution decreases.
This simple example illustrates the magnitude of computation required and why more system design teams are employing a TLM-based methodology.
In this methodology, we still start with the traditional methods used to capture the customer requirements: Sometimes, the product requirements are obtained directly from a customer.
More likely, the requirements are captured through the research of a marketing group. The TLM model is usually written by an architect or architecture group.
This model captures the product specification or system-critical parameters. In an algorithmic intensive system, the TLM model will be used to refine the system algorithms. The TLM model is refined further as software design and development and hardware verification environment development progresses. The TLM has several use cases: Architectural modeling 2.
Algorithmic modeling 3. Virtual software development platform 4. Functional verification 5. Hardware refinement We will further discuss these use cases in the next few sections. However, the TLM creates high value benefits including: The following section discusses in more detail the benefits that TLM modeling will bring to your organization. Refining in a software environment provides a much friendlier environment for debug compared to RTL debug.
In addition, a software model within the context of an ESL methodology provides the architect a platform for asking and answering a series of questions such as: How sloppy can we get with our arithmetic and have the algorithm still work?
Can I get away with a software-only solution? Can I use a lower clock rate for my processor with the resulting power savings if I implement this algorithm with a hardware co-processor? After completing the design of the actual algorithm getting it to work , the algorithm architect usually refines the algorithm from a floating-point implementation to a fixed-point supported by SystemC implementation for hardware implementation.
This architect also partitions the algorithm between hardware and software. An architect with broad experience will understand the different tradeoffs between software and hardware and will shape the algorithm implementation to be very implementable in the chosen space for instance minimizing memory use for hardware implementation.
This work is usually augmented with libraries for a particular application space such as a fixed-point library, a digital signal processing library, and others. It is also about bus performance analysis, and other initial refinements based on a power management concept. This modeling also includes existing intellectual property and designs as well as other product-based technical and management critical parameters and trade-offs. Some of the questions asked during this activity are: Will we require multiple busses or a multitiered bus concept?
How would a lower clock rate or less capable processor affect performance? This activity can be performed using SystemC or another language that supports modeling or simulation concurrency. These teams have been forced to develop a custom simulation kernel to support concurrency. These generators are based on an estimate of the bus traffic generated by the non-critical elements. As the model is refined, the blocks are refined to add the details required to start running software.
There are several vendors of EDA tools that have offerings that can help accelerate this activity. During this activity, the following questions are sometimes asked and answered: Does the software have the necessary control and observably to meet the customer requirements?
We call this technique direct execution. Even as the software is refined and OS calls are required, additional techniques can be used to enable direct execution. This specification accelerates hardware development. Alternatively, activities can be focused on refinement for behavioral synthesis with even greater schedule and productivity improvements. Some of the questions asked during this set of activities are: Refining the specification for hardware designers eliminates potential overdesign.
Many times during the development process, an RTL designer will ask an architect specific questions where the answer will significantly or even slightly affect performance.
When the architect is asked about option A or option B, he or she will answer yes or both because of the absence of information, thus adding complexity. With a model that can be refined, the architect can model the affect of A and B and possibly come back with the answer that neither option helps. The refined model saves design time, verification time, and silicon area. Unfortunately, as systems become more complex, the functional specs can be measured in feet not inches of paper.
Obviously, any process requiring a natural language like English or German, Chinese, French, etc. We have added a new term at least for us: The goal of this activity is to answer a few big questions: We have purposely used the term, system architecture, because this involves integrating at least the lowest level software and a hardware model. Verification teams are always complaining that they are not allowed to start until too late.
Some of the reason for this trend is that management is reluctant to assign resources to project activities that will not show results or progress until much later in the project. The TLM modeling activity allows a target for early development. Many of the newer verification methodologies such as OVM and VMM make heavy use of constrained-random test stimulus generation. Some of these requirements are: SystemC 15 1. SystemC is not a panacea that will solve every design productivity issue.
However, when SystemC is coupled with the SystemC Verification Library, it does provide in one language many of the characteristics relevant to system design and modeling tasks that are missing or scattered among the other languages. Several languages have emerged to address the various aspects of system design.
The hardware description languages, VHDL and Verilog, are used for simulating and synthesizing digital circuits. Vera, e, and recently SystemVerilog are the languages of choice for functional verification of complex application-specific integrated circuits ASICs.
SystemVerilog is a new language that evolved from the Verilog language to address many hardware-oriented system design issues. Each language occasionally finds use outside its primary domain, as the overlaps in the figure illustrate. IEEE When a language is standard and open to the industry, then a wide array of benefits are available.
These benefits include access to a set of commercial and freeware-based tools and support. Today, the OSCI continues this effort. The most notable effort is the standardization of a set of TLM interfaces. It is provided freely from the OSCI website at www. These are the skills that enable a great SystemC modeler. Not so obviously to some, the language needs to support concurrent simulation we will talk about this extensively later in the book.
The language must also support a series of additional productivity features. Any model needs to execute relatively swiftly. A model is never fast enough, so what is fast enough. One can look at the requirements for model speed when used for common ESL purposes like early software development. No modeling language can make up for inefficient modeling practices. As the reader may have guessed by now, developing a model is different than developing an application program. The difference is that in an ESL model, the 1.
SystemC 17 code modules need to appear as if they are executing in parallel or concurrently. When a digital system is running, then many, many computations are running at the same time or are running concurrently. SystemC provides a simulation kernel to give this illusion of concurrency.
This feature, as well as several others, helps manage the complexity of the model. In addition, SystemC is supported by a large and growing ecosystem of commercial suppliers. Some of these tools include integrated development environments IDEs , performance analysis tools, and lint tools to illustrate just a few.
There are many more tools available from leading software tool vendors for a small fee. These tools come with varying degrees of support. Many of the groups using SystemC are large organizations that require ESLspecific productivity tools and technology as well as significant support.
The last time we counted, the list was over 40 companies and growing. The tools range from co-simulation with their HDL simulators to behavioral synthesis tools.
The availability of graphic algorithms, DSP algorithms, and a plethora of other application libraries make the writing of initial models very easy.
An extreme example is the use of an H. It must support the easy substitution of one communication implementation with another without changing the interface to that implementation. You will then be equipped to charge into the brave new world of ESL and TLM modeling and to bring about significant changes in your organization, company, and the industry.
This chapter presents an overview of the SystemC language elements. Details are discussed in-depth in subsequent chapters. Despite our best efforts not to use any part of the language before it is fully explained, some chapters may occasionally violate this goal due to the interrelated nature of SystemC. This chapter briefly discusses the major components of SystemC and their general usage and interactions as a way of giving context for the subsequent chapters.
The following diagram, Fig. As a form of roadmap, we have included a duplicate of this diagram at the beginning of each new chapter. Bolded type indicates the topics discussed within that chapter.
For the rest of this chapter, we will discuss all of the components within the figure that are outlined in bold; but first, we will discuss the mechanics of the SystemC development environment. The primary application area for SystemC is the design of electronic systems. However, SystemC also provides generic modeling constructs that can be applied to non-electronic systems1 Fig. The components of a SystemC environment include a: The download contains scripts and make files for installation of the SystemC library as well as SystemC source code, examples, and documentation.
The install scripts are compatible with the supported operating systems, and the scripts are relatively straightforward to execute by carefully following the documentation. At this time, the OS list is limited by the use of minor amounts of assembly code that is used for increased simulation performance in the SystemC simulation kernel. For beginners, this OS and compiler list should be considered exhaustive.
The flow for compiling a SystemC program or design is very traditional and is illustrated in Fig. Most other compilers will be similar. Each file set usually consists of two files, typically with standard file extensions. We use. Note that the compiler and linker need to know two special pieces of information.
First, the compiler needs to know where the SystemC header files are located. Second, the linker needs to know the location of the compiled SystemC libraries. This information is typically passed by providing an environment variable named 2. The downloadable examples available from our web site include a makefile setup for Linux and gcc. The resulting file is usually referred to as an executable, and it contains the SystemC simulation kernel and your design functionality.
The rest of you now have an overview of how to compile and run the code examples in this book as well as your own SystemC creations. Everyone is now ready to dive into the language itself.
For some installations, dynamic libraries may also be referenced if using the SystemC Verification library. SystemC provides several hardware-oriented constructs that are not normally available in a software language; however, these constructs are required to model hardware.
This section looks at SystemC from the viewpoint of the hardware-oriented features. The major hardware-oriented features implemented within SystemC include: Global time is advanced within the kernel.
SystemC provides mechanisms to obtain the current time and implement specific time delays. To support ease of 2. Since many applications in SystemC do not require a clock but do require a notion of time , the clock discussion is deferred to later chapters of the book.
Additionally, clocks do not add to the fundamental understanding of the language. By the later chapters, you should be able to implement the clock class yourself with the fundamentals learned throughout the book. SystemC provides hardware-compatible data types that support explicit bit widths for both integral and fixed-point quantities. Furthermore, digital hardware requires non-binary representation such as tri-state and unknowns, which are provided by SystemC. Finally, hardware is not always digital.
SystemC does not currently directly support analog hardware; however, a working group has been formed to investigate the issues associated with modeling analog hardware in SystemC. For those with immediate analog issues, it is reasonable to model analog values using floating-point representations and provide the appropriate behavior.
SystemC provides several constructs for implementing hardware hierarchy. Hardware designs traditionally use blocks interconnected with wires or signals for this purpose. For modeling hardware hierarchy, SystemC uses the module entity interconnected to other modules using channels. The hierarchy comes from the instantiation of module classes within other modules.
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